It is assumed that a bit string N including number of bits n is used as the data bits to indicate the shift count for a given sequence D of data bits, viz., the number of bit positions or digits by which the digits in the given data bit sequence D are to be shifted. As well known in the art, the shift counts available with such a data bit string N total to 2.sup.n-1 counts inclusive of a zero-bit shift since a 2.sup.n -bit shift is equivalent in effect to the zero-bit shift. The data bits of such a bit string N may be solely indicative of the shift count or may include not only the bits indicative of the shift count but also a bit indicating the direction in which shifts are to be made within the data bit sequence D. Where the bit string N is represented in the two's complement system, each of the possible numbers which can be expressed by the bit string N is given as: ##EQU1## where m.sub.i represents the individual digits forming the bit string N.
From this Eq. 1 it will be seen that the numbers which the bit string N can express consist of a set of integers ranging from -2.sup.n-1 to +(2.sup.n-1) inclusive of zero. Where such a data bit string N includes a sign bit assigned to the direction of shift, there are available two different shift making techniques. One technique is to make left and right shifts each by number of n bit positions in a shifter circuit with left-shift and right-shift potentialities. The other is to make use of the rotating or carry-around function of, for example, a barrel shifter to effect an N-bit shift in one direction and a shift by a 2.sup.n-1 -N number of bit positions in the other direction, thus making virtual left and right shifts each by number n of bit positions. Of these two shift making techniques, the latter is generally preferred for ease of designing and constructing the shifter circuit to implement the particular technique.
On the other hand, in a dyadic operation in which two operands are to be arithmetically added together in a floating-point arithmetic routine, the digits of the mantissa of the operand with the lesser exponent part are shifted by a number of bit positions corresponding to the difference between the numbers of digits of the respective exponent values of the two operands. Thus, upon comparison between the respective exponent values of the two operands, a positive shift count can always be obtained by subtracting the smaller exponent value from the larger in the floating-point arithmetic routine. In the case of a high-speed floating-point arithmetic operation, sophisticated techniques are required for executing the comparison and subtraction by parallel processing for the scaling of the dyadic operands. Adoption of such parallel processing schemes inevitably results in a penalty of added hardware components of the register or accumulator using the high-speed floating-point arithmetic format.
The high-speed floating-point arithmetic routine has another problem in that, with the comparison and subtraction of the two exponent values performed in parallel, the subtracting operation proceeds without respect to the relationship in magnitude between the respective exponent values of the two operands. It may thus happen that the larger one of the exponent values is subtracted from the smaller although the direction of shift of the mantissa of the word number to be scaled is fixed. Assume furthermore that the smaller of two number words each of which is to result in a negative number represented by a two's complement is to be brought into a shifter circuit to effect an .vertline.N.vertline.-bit shift of the number word in the shifter circuit. If, in this instance, the n.sup.th bit m.sub.n of the bit string N equals 1, there holds the relationship EQU .vertline.N.vertline.=N+1 Eq. 2
so that it is necessary to obtain from this Eq. 3 the absolute value of the two's complement of the number word brought into the shifter circuit. This means that a procedure similar to that used for making a shift by a 2.sup.n-1 -N number of bit positions in a barrel shifter as hereinbefore discussed is required to be followed using a rotation shifting technique, since ##EQU2##
Such a shifting procedure may be performed by a shifter circuit which has an N-bit shift stage and a single-bit shift stage as taught in, for example, Japanese Provisional Patent Publication No. 59-0079495. As well known in the art, a number to be shifted is ordinarily longer in word length than a bit string to be used as the data predominant over the shift count. More hardware components are for this reason required for implementing the single-bit stage of the split-type shifter circuit. In addition, the circuit structure including the separate N-bit and single-bit shift stages of such a shifter circuit is likely to result in prolonged and intricately routed signal transmission paths of the split-type shifter circuit. Implementation of such a circuit structure on a semiconductor integrated circuit chip therefore places significant limitations in the performance efficiency achievable of the circuit, especially where the circuit is used in a dynamic configuration.
It is accordingly an important object of the present invention to provide a useful solution to the problems which have thus far been inherent in the bidirectional shifting techniques with rotational features and the techniques for controlling the shift counts as required in effecting, for example, the scaling of dyadic operands in floating-point arithmetic routines as hereinbefore proposed and put into practice. It may be noted that the problems of the prior art shifting and scaling techniques include the limitations in the operating speeds available therefor, the requirement for additional hardware components and the resultant complexity of the shifter circuit. All these problems are encountered whether the operation N+1 as above discussed is to be effected in an arithmetic circuit or in a shifter circuit which has separate N-bit and single-bit shift stages.